package SimpleLACore

import chisel3._
import chisel3.util._

class SimpleLACoreWrapRAM extends Module{
  val io = IO(new Bundle {
    val ipi = Input(Bool())
    val interrupt = Input(UInt(8.W))
    val debug = Output(new DebugPort)
    val inst = Flipped(new Bundle {
      val en     = Input(Bool())
      val addr    = Input(UInt(32.W))
      val rdata   = Output(UInt(32.W))
    })
    val data = Flipped(new Bundle {
      val en     = Input(Bool())
      val wen   = Input(UInt(4.W))
      val addr    = Input(UInt(32.W))
      val wdata   = Input(UInt(32.W))
      val rdata   = Output(UInt(32.W))
    })
  })
  val core = Module(new SimpleLACore(false))
  core.io.ipi := io.ipi
  core.io.interrupt := io.interrupt
  io.debug <> core.io.debug
  io.data.en := core.io.data.req.valid && !core.io.data.req.bits.cacop && !core.io.data.req.bits.preld
  io.inst.en := core.io.inst.req.valid
  io.data.addr := core.io.data.req.bits.addr
  io.inst.addr := core.io.inst.req.bits.addr
  io.data.wen := core.io.data.req.bits.wen
  io.data.wdata := core.io.data.req.bits.wdata
  core.io.inst.resp.valid := core.io.inst.req.valid
  core.io.inst.resp.bits := io.inst.rdata
  core.io.data.resp.valid := core.io.data.req.valid
  core.io.data.resp.bits := io.data.rdata
}
